ParCoreLab Seminars
Dr. Nehir Sönmez
Barcelona Supercomputing Center
8 November 2021
Dr. Nehir Sonmez holds a PhD in Computer Engineering (2012) from the Technical University of Catalonia (UPC), Spain, an MS degree from Bogazici University, Turkey (2006) and a BS degree from Syracuse University USA (2003). He is currently a senior researcher in the High Performance Domain-Specific Architectures research group at BSC, where he is the coordinator of the EuroHPC-JU eProcessor project. He is also active in the architecture design and verification efforts in EPI and DRAC projects, on RISC-V processors and vector accelerators. His other research interests include reconfigurable computing, computer architecture and multicores, transactional memory, disaggregated computing, and database acceleration.
Research paper covered during the seminar:
A RISC-V Simulator and Benchmark Suite for Designing and Evaluating Vector Architectures, TACO ’17
Dr. Luc Jaulmes
Barcelona Supercomputing Center
4 October 2021
Luc Jaulmes received the double MSc degree in engineering in computer science from Ecole Polytechnique, Paris and the Royal Institute of Technology (KTH), Stockholm, specializing in computer architecture. He received the PhD degree in the Barcelona Supercomputing Center (BSC) in 2019. His thesis focused on the resilience of high performance computing (HPC) applications and memories on extreme scale machines, using novel programming models, runtime systems and runtime-aware architectures.
Research paper covered during the seminar:
Dr. Aleksandar Ilic
INESC-ID
4 October 2021
Aleksandar Ilic (PhD’14) is an Assistant Professor at the Instituto Superior Técnico (IST), Universidade de Lisboa, and a Researcher of INESC-ID, Lisbon, Portugal. He has contributed to more than 50 international journal and conference publications, and received several Excellence in Teaching awards. Besides his teaching experience, he has organized and participated in more than 20 roofline-related tutorials, invited talks and seminars held at different scientific events, such as SC, ISC, Intel oneAPI Dev Summits, PACT etc. The integration of his scientific contribution (Cache-aware Roofline Model) in industry software tools (Intel Advisor) received the HiPEAC Tech Transfer award. His research interests include high-performance and energy-efficient computing and modeling of parallel heterogeneous systems.
Research papers covered during the seminar:
Dr. Milind Chabbi
Uber Technologies, Inc.
13 July 2021
Milind Chabbi conducts research in the areas of high-performance parallel computing, shared- memory synchronization algorithms, performance analysis tools, and compiler optimizations. He is currently employed as a senior researcher at Uber Technologies in Palo Alto, USA and is also the president of his independent research company Scalable Machine Research. Previously Milind worked at Baidu Research, Hewlett Packard Labs, and Microsoft. Milind Chabbi obtained his doctoral degree in computer science from Rice University working in the areas of software tools and algorithms for high-performance parallel computing. Milind has published over 30 conference and journal publications, received numerous best paper awards, and owns eight USPTO patents.
Research papers covered during the seminar:
Dr. Tan Nguyen
Lawrence Berkeley National Laboratory
21 June 2021
Tan Nguyen is a research scientist at Lawrence Berkeley National Laboratory. His recent research focuses on performance analysis and code optimizations for various processor architectures, including multi- and many-core CPUs, GPUs, FPGAs, and CGRAs. He is also interested in compiler analysis and code generation, programming models and runtime systems for scientific applications. Nguyen received his Ph.D. degree in Computer Science from University of California, San Diego in 2014.
Research papers covered during the seminar:
- The Performance and Energy Efficiency Potential of FPGAs in Scientific Computing, 2020 IEEE/ACM PMBS
- Plasticine: A reconfigurable architecture for parallel patterns, ISCA ’17
- Fast Stencil-Code Computation on a Wafer-Scale SC’20 Processor
- In-Datacenter Performance Analysis of a Tensor Processing Unit, ISCA ’17
Dr. Mohamed Wahib
AIST/TokyoTech Open Innovation Laboratory
25 May 2021
Mohamed Wahib is a senior scientist at AIST/TokyoTech Open Innovation Laboratory, Tokyo, Japan. Prior to that he worked as a researcher in RIKEN Center for Computational Science (RIKEN-CCS). He received his Ph.D. in Computer Science in 2012 from Hokkaido University, Japan. Prior to his graduate studies, he worked as a researcher at Texas Instruments (TI) R&D labs in Dallas, TX for four years. His research interests revolve around the central topic of “Performance-centric Software Development”, in the context of HPC. He is actively working on several projects including high-level frameworks for programming traditional scientific applications, as well as high-performance AI and data analytics.
Research papers covered during the seminar:
- ParDNN: An Oracle for Characterizing and Guiding Large-Scale Training of Deep Neural Networks, HPDC’21
- Scaling Distributed Deep Learning Workloads beyond the Memory Capacity with KARMA. SC’20
- A Study of Single and Multi-device Synchronization Methods in Nvidia GPUs. IPDPS’20